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| PM8379 CTS 20x4G Advance 20-Port 4.25 Gbit/s FC-AL Cut-Through Switch The CTS 20x4G is designed to interface directly to Fibre Channel disk drives in a storage array. It can interface directly to optics or to cables at the ingress/egress point of an enclosure and is able to determine if an incoming frame is destined for a drive within that enclosure. After determining which port is associated with the frames recipient, a cut through operation to that port is performed thereby significantly reducing system latency and improving performance. The CTS 20x4G provides unique disk isolation features that significantly increase total system availability, reliability, and serviceability. * Built-in self test capability with FC Frame Generator/Comparator. * Supports a 106.25 MHz, 40-bit (20 receive + 20 transmit) DDR parallel interface that acts as a 21st port. This flexible interface enables external functions such as enclosure management or other user-proprietary functions to be implemented using a low cost FPGA. CUT-THROUGH SWITCHING * Integrated cut-through switching and arbitration management enables up to 200% improvement in EDR and IOPS. * Parallel arbitration supported with arbitration priority and access fairness preserved. * Automatic or CPU controlled initialization of AL_PA table. * Supports dynamic half duplex, half/full duplex operation, LPSM transfer state, multicast/broadcast (OPNy). FEATURES GENERAL * 20 independent rate selectable 1.0625, 2.125 or 4.25 Gbit/s physical interfaces. * Register and software compatible to the PM8368 PBC 18x2G, PM8369 PBC 18x4G, PM8372 PBC 4x2G and PM8377 PBC 4x4G. * Compliant to FC jitter specifications on a per-port basis. * Supports single-ended or differential 106.25 MHz reference clock. * Per port monitoring and diagnostics: * LPSM Monitoring on each port. * Disk isolation and per port serial loopback. * Configurable Digital Loss of Link: analog LOS Detect, 8B/10B disparity errors/error rate, CRC errors/error rate, word synchronization error/error rate, and compliant frequency of comma patterns detected (configurable thresholds for each with corresponding pin interrupts). BLOCK DIAGRAM CTS Logic Arb Mgmt Cut Thru Mgmt AL_PA Table Frame Generator Frame Comparator RDIN[0] RDIP[0] RX SERDES RDIN[1] RDIP[1] RX FIFO TX FIFO TDON[0] TDOP[0] RX FIFO TX FIFO TX SERDES TDON[1] TDOP[1] RDIN[19] RDIP[19] RXCLK RXD[19:0] RX FIFO TX FIFO TDON[19] TDOP[19] RX FIFO TXD[19:0] TXCLK JTAG CDRU CPU CONTROL MDIO_SDA REFCLK_P EXTCAP REFCLK_N MDC_SCL CLK_SEL TWI_SEL DLOLB TDI TRSTB FULL_RATE DEVBYPSB RESETB INTRB DLOLBYP_MSK TRUST_MODE RECEQUALIZ[1:0] MON_BYP_PORT REFCLK_S PREEMPH[1:0] PMC-2031144 Issue 2 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE DVPRTAD[5:0] (c) Copyright PMC-Sierra, Inc. 2004. All rights reserved. BYPASS[20:0] OENB TCK TDO TMS PM8379 CTS 20x4G 20-Port 4.25 Gbit/s FC-AL Cut-Through Switch HIGH-SPEED INTERFACE * Independent per-channel selectable high-speed outputs support 8 levels of programmable pre-emphasis and 8 levels of output swing. Selectable preemphasis counteracts dielectric losses and allow maximum reach on printed circuit boards. * Independent per-channel selectable high-speed inputs support 30 levels of programmable receive equalization for improved signal integrity. * Integrated 100 differential termination for signal integrity, smaller solution footprint, and lower component count. TEST AND CONTROL * Supports optional 2-pin serial management interface using selectable Two-Wire Interface (TWI) protocol for configuration and diagnostic access. * Digital Loss of Link (DLOLB) detect outputs for monitoring individual or multiple links. DLOLB can be programmed to indicate excessive 8B/10B code error rate, loss of synchronization, loss of signal, CRC32 errors, or comma density. * External control pins can be overridden by registers. * Interrupt output to flag changes in bypass state and DLOLB error conditions. * Supports built-in self-test (BIST) via internal Fibre Channel pattern generation and checking. * Supports internal serial loop back modes for each port for testing and debugging. * Provides a standard 5-signal IEEE 1149.1 JTAG test port for boundary scan board testing purposes. PHYSICAL * 0.13 um (1.2 V Core and 3.3 V I/O supply) CMOS technology. * 27 mm x 27 mm 352-pin CSBGA+. * Ultra-low operating power of 6.5 W typical with all 20 channels active at 4.250 Gbit/s. APPLICATIONS * * * * * * * * SBOD Storage Systems. MBOD Storage Systems. RAID Storage Systems. JBOD Storage Systems. FC to SATA Storage Systems. FC-AL Nodes. Fibre Channel Hubs. 1.0625, 2.125, and 4.25 Gbit/s Backplanes. TYPICAL APPLICATIONS Fibre Channel Disk Enclosure 18 Disk SBOD/MBOD/JBOD Disk 0 * * * Note: Each signal contains one Bypass and one FC Port line. Disk 4 1.0625 or 2.125 or 4.25 Gbit/s FC Link Link Card for HDD Port A FC Port * * * Link Card for HDD Port B FC Port Disk 5 PM8378 CTS 20x4G * * * Optics PM8378 CTS 20x4G Optics 1.0625 or 2.125 or 4.25 Gbit/s FC Link Disk 10 * * * Disk 11 * * * Disk 17 18 Disk SBOD/MBOD/JBOD Disk 0 * * * Note: Each signal contains one Bypass and one FC Port line. Disk 4 Link Card for HDD Port A * * * Link Card for HDD Port B Disk 5 PM8378 CTS 20x4G * * * PM8378 CTS 20x4G Disk 10 * * * Disk 11 Additional Disk Enclosure * * * Additional Disk Enclosure Disk 17 Head Office: PMC-Sierra, Inc. 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 1.604.415.6000 Fax: 1.604.415.6200 To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com PMC-2031144 (a2) For a complete list of PMC-Sierra's trademarks, see our web site at http://www.pmc-sierra.com/legal/. Other product and company names mentioned herein may be the trademarks of their respective owners. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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